Tran Duc Anh

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I am a motivated RTL Design & SoC Engineer with hands-on experience in Verilog/SystemVerilog, FPGA development, and ASIC design fundamentals.

My interests include digital hardware design, RISC-V based systems, RTL-to-GDSII flow, and hardware–software co-design on Linux.

Profile

Education
Ho Chi Minh City University of Technology (VNU-HCMUT)
Major: Computer Engineering (2023 – 2027)
GPA: 3.5 / 4.0

Career Objective
Seeking opportunities to apply strong knowledge in RTL design, SoC architecture, and hardware verification to contribute to high-performance semiconductor solutions.

Projects

RTL-to-GDSII Flow & RISC-V System Integration

• Designed digital logic modules using Verilog HDL
• Implemented RTL-to-GDSII flow using OpenLane & SkyWater 130nm PDK
• Executed synthesis, floorplanning, CTS, and routing
• Configured PetaLinux for RISC-V based system
• Analyzed interaction between RTL/SoC and Linux OS

True Random Number Generator (TRNG)

• Designed TRNG using flip-flop metastability
• Integrated memory-mapped control interface
• Built FPGA system in Vivado and software in Vitis Embedded
• Verified randomness and system functionality on hardware

Skills

Programming / HDL

Verilog, SystemVerilog, C, C++, Assembly, TCL

EDA & Tools

Vivado, Vitis Embedded, Vitis HLS, OpenLane, Klayout, STM32CubeIDE, Altium Designer, MATLAB, PSpice, Petalinux

Technical Knowledge

RTL Design, FPGA Development, ASIC Flow, Hardware–Software Co-design, Embedded Linux

Contact

📞 0824 244 858
📧 20211.tranducanh.dbk@gmail.com
📍 Ho Chi Minh City, Vietnam

• GitHub
• Email